1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing such semiconductor device, and more particularly to an integrated circuit (IC) device with an improved endurance against stress induced failure and a method of manufacturing such IC device.
2. Description of the Related Art
With a remarkable development in miniaturization and increased degree of integration of semiconductor devices such as memory IC devices represented by D-RAMs (dynamic random access memory), the size of active regions (functional regions) and interconnections for such active regions is made increasingly smaller. That are, as the number of active regions on a semiconductor chip of certain size increases (i.e., reduction in size of the active regions), the size of the interconnections for connecting these active regions must necessarily be reduced or multilayered.
As the interconnections are formed in smaller size, their characteristic requirements become all the more stringent. That is, in addition to the problems of reduced electric resistance causing voltage drops, electromigration resistance due to the application of high current densities, ohmic contact and contact at respective active regions or shrunk portions of interconnections, adhere to insulating films (insulating layers) endurance against stress induced failure must also be taken care of.
Stress induced failure is attributable to thermal expansion coefficient mismatch between a polycrystalline metal or single crystal metal forming the electrode line and a passivation film for covering such polycrystalline metal or single crystal metal. Stress induced failure is a phenomenon that the electrode line fails during use of a semiconductor device due to a thermal stress caused when the passivation film is heated to high temperatures for its formation and then cooled down to room temperature.
That is, stress induced failure is a line void caused in the course of relieving the thermal stress due to thermal expansion coefficient mismatch between the electrode line and the passivation film. It occurs at grain boundaries, and it has been found out that the ruptured (cut) surface is a (111) plane in the case of an Al-Si line.
Further, in the case of a multilayered line, a hole (via hole) is arranged in an insulating layer interposed between different line layers and this via hole is filled by a conductive material by, e.g., a bias sputtering, a chemical vapor deposition (CVD) method, a CVD-W method, or a CVD-Al method to achieve inter-line connections. However, as the line width becomes narrower, so does the diameter of the via hole, and this causes high density current to flow in the interconnections, thereby imposing the problem of impaired electromigration resistance.
In view of the electromigration resistance that must be improved as the electrode line is increasingly smaller, attempts to arrange (form) the electrode line with a single crystal metal are disclosed, e.g., in Japanese Patent Unexamined Publication No. 37050/1989. However, the electrode line made of a single crystal metal is not sufficiently reliable in terms of impurity elements from the passivation film with which the surface of the electrode line is covered, diffusion of a gas, and moisture resistance and endurance against stress induced failure of the electrode line.
As a measure to improving the endurance against stress induced failure of the polycrystalline electrode line, attempts have been made to suppress thermal stresses by forming the passivation film at low temperatures and to reinforce its grain boundaries where voids occur by using an alloy represented by an Al-Si-Cu alloy line thereby to precipitate an intermetallic compound at these grain boundaries. However, they have not been satisfactory yet.
There are other electrode line arrangements. For example, Japanese Patent Unexamined Publication Nos. 308348/1989 and 47951/1988 disclose an arrangement that a polycrystalline metal electrode line is coated with a high melting point metal or a silicide or a nitride of the high melting point metal. However, in such an arrangement, the coated high melting point metal element diffuses through the grain boundaries of the polycrystalline metal, thereby increasing the resistivity of the electrode line or impairing its electromigration resistance and endurance against stress induced failure due to precipitations at the grain boundaries. As a result, the electrode line becomes susceptible to lose its reliability. For example, in the case of an electrode line having W coated on a line composed of an Al-2 wt % Si alloy, no line failure of the coated W film was observed while apparent line failures of the Al-Si line inside were detected during stress induced failure tests, whereby it has been verified that the electrode line was not sufficiently reliable.
With respect to improvement in electromigration resistance, attention has been given to the crystal orientation of a thin film constituting the electrode line. And, the relationship between the electromigration resistance and the integrated intensity ratio (f.sub.(111) /f.sub.(200)) of the (111) plane to the (200) plane obtained by an X-ray measurement indicates that the larger the ratio is, the better the electromigration resistance is (S. Vaidya et al., "Thin Solid Film", 75 (1981), pages 253ff). However, this publication does not refer to the extent of (111) orientation itself nor does it discuss endurance against stress induced failure at all.
As described above, to further reduce the size of the elements and increase the degree of integration of the conventional semiconductor devices, it is desired that the problems not only of providing the electrode line with sufficient electromigration resistance and endurance against stress induced failure but also of providing sufficient safeguards to the impaired electromigration resistance and endurance against stress induced failure due to diffusion of impurities and water from the coated passivation film be well taken care of.
Further, the electrode line must be highly formable, highly resistant to various thermal and chemical treatments during manufacturing processes, and easy to be manufactured or formed thereby to allow highly reliable semiconductor devices to be obtained consistently.
With respect to means for deposition of a single crystal film, a method such as an ion beam sputtering method, a thermal CVD method, or an ion cluster beam deposition method is generally employed to directly deposit a metal film on a (111) Si substrate, and this metal film is subjected to, e.g., a photoetching process to pattern into a line. However, since it is difficult to deposit a predetermined single crystal film on to an interlayer insulating film such as SiO.sub.2 and the relationship between the crystal orientation and the single crystal line direction is neglected in the actual process, the means for depositing the single crystal electrode line is likewise afflicted by the problem of impaired electromigration resistance and endurance against stress induced failure.
An object of the present invention is therefore to provide a semiconductor device having an electrode line whose electromigration resistance and endurance against stress induced failure are improved.
Another object of the present invention is to provide a semiconductor device allowing the reduction in size of an active region; i.e., high density arrangement.
Still another object of the present invention is to provide a semiconductor device which is highly reliable functionally.
Still another object of the present invention is to provide a method of easily manufacturing a semiconductor device which allows the reduction in size of an active region; i.e., high density arrangement.
Still another object of the present invention is to provide a method of easily manufacturing a semiconductor device which is highly reliable functionally.